Its 140 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports resolutions up to SXGA (1280 . 1024 at 75 Hz). The AD9883A includes a 140 MHz triple ADC with internal 1.25 V reference, a PLL, and programmable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and HSYNC and COAST signals. Three-state CMOS outputs may be powered from 2.5 V to 3.3 V. The AD9883A’s on-chip PLL generates a pixel clock from HSYNC and COAST inputs. Pixel

A TCP/IP stack with integrated device driver and example code is provided in VisualDSP++® release 4.0. This evaluation kit was designed with an emphasis on modularity and expandability. With this EZ-KIT Lite, users can learn more about Analog Devices ADSP-BF537 hardware and software development and quickly prototype applications. The EZ-KIT Lite includes an ADSP-BF537 processor desktop evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment that i

Populate R406 and R407 with 0 . resistors and remove R415 and R416 to disconnect the default clock path inputs. In addition, populate C405 and C406 with a 0.1 .F capacitor and remove C409 and C410 to disconnect the default clock path outputs. The AD9515 has many pin- strappable options that are set to a default mode of operation. Consult the AD9515 data sheet for more information about these and other options. PDWN To enable the power-down feature, short P303 to the on position (AVDD) on the PDW

The AD9551 Revision D evaluation board is a compact, easy to use platform for evaluating all features of the AD9551 multiservice clock generator. The AD9551 accepts one or two reference input signals to synthesize one or two output signals. The AD9551 uses a fractional-N PLL that precisely translates the reference frequency to the desired output frequency. The input receivers and output drivers provide both single-ended and differential operation. Reference conditioning and switchover circuitry

All trademarks are the property of their respective holders. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ADSP-2186 FUNCTIONAL BLOCK DIAGRAM ADSP-2100 BASE SHIFTERMACALU ARITHMETIC UNI

The AD9272/AD9273 data sheet, available at provides additional information and should be consulted when using the evaluation board. All documents and software tools are available at For any questions, send an email to highspeed.converters@analog.com. TYPICAL MEASUREMENT SETUP Adobe Systems 07782- 001 Figure 1. AD9272-65EBZ/AD9272-80KITZ/AD9273-50EBZ Evaluation Board and HSC-ADC-EVALCZ Data Capture Board TABLE OF CONTENTS Features ..................................................................

Its architecture is similar to that of Analog Devices’ ADSP-2100 family of fixed-point DSP processors. Fabricated in a high-speed, low-power CMOS process, the ADSP-21020 has a 30 ns instruction cycle time. With a high- performance on-chip instruction cache, the ADSP-21020 can execute every instruction in a single cycle. The ADSP-21020 features: • Independent Parallel Computation Units The arithmetic/logic unit (ALU), multiplier and shifter perform single-cycle instructions. The units are archite

02062-9106 a Copyright Information ©2007 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Limited Warranty The EZ-KIT Lite evaluation system is warranted against defects in materials and workmanship for a period of one year from the date of purchase from Analog Devices or from an authorized dealer. Disclaimer Analog Devices, Inc. reserves the right to change this product

Ensure that Jumper JMP3 is positioned for PC control. 2. Verify that all five jumpers are in place on Connector P2. 3. Set the S1, S2, and S3 dip switch positions to high. 4. Select 622.08 MHz for the input frequency in the REF A (MHz) box in the main window of the evaluation software (see Figure 4 and the Reference Input Boxes section for more information). 5. Select 622.08 MHz for the output frequency in the Output Loop Config: box in the main window of the evaluation software (see Figure 4).