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18-bit common I/O architecture • 3.3V core power supply (VDD) • 2.5V/3.3V I/O power supply (VDDQ) • Fast clock-to-output times — 3.5 ns (for 166-MHz device) • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous Output Enable • Available in JEDEC-standard lead-free 100-Pin TQFP package • “ZZ” Sleep Mode option Selection Guide Functional Description[1] The CY7C1298H SRAM integrates 64K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:B], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penalizing system performance. The CY7C1298H operates from a +3.3V core power supply while all outputs operate either with a +2.5V or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. 166 MHz 133 MHz Unit Maximum Access Time 3.5 4.0 ns Maximum Operating Current 240 225 mA Maximum CMOS Standby Current 40 40 mA Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-05665 Rev. *B Revised July 5, 2006 [+] Feedback CY7C1298H Functional Block Diagram ADDRESS REGISTER ADV CLK BURST COUNTER AND LOGIC CLR Q1 Q0 ADSC BWB BWA CE1 DQB, DQPB BYTE WRITE REGISTER DQA , DQPA BYTE WRITE REGISTER ENABLE REGISTER OE SENSE AMPSMEMORY ARRAY ADSP 2 A[1:0] MODE CE2 CE3 GW BWE PIPELINED ENABLE DQs, DQPA DQPB OUTPUT REGISTERS INPUT REGISTERS E OUTPUT BUFFERS DQB , DQPB BYTE WRITE DRIVER DQA, DQPA BYTE WRITE DRIVER SLEEP CONTROL ZZ A0, A1, A Document #: 38-05665 Rev. *B Page 2 of 16 [+] Feedback CY7C1298H Pin Configurations 100-Pin TQFP Top View NC NC NCVDDQ VSSQ NC NC DQB DQB VSSQVDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NCVSSQVDDQ NC NC NC 31 MODE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 A A CE1 3299 A A 33 98 A 34 CE2 97 A 35 NC 96 36 A1 NC 95 37 A0 BWB 94 3840 NC/72M 41 VDD CY7C1298H BWA 93 CE3 92 91 VDD 90 VSS CLK 89 88 GW 39 NC/ 36M VSS 42 NC/18M 43 NC/9M 4487 BWE A 45 OE A 86 46 ADSC A 85 47 A ADSP 84 48 A ADV 83 49 NC/ 2M A 82 50 NC/ 4M 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 A A NC NC VDDQVSSQ NC DQPA DQA DQA VSSQVDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQVSSQ DQA DQA NC NC VSSQVDDQ NC NC NC Document #: 38-05665 Rev. *B Page 3 of 16 [+] Feedback CY7C1298H Pin Descriptions Pin Type Description A0, A1, A Input- Synchronous Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] are fed to the two-bit counter. BW[A:B] Input- Synchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. GW Input- Synchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW[A:B] and BWE). BWE Input- Synchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. CLK Input- Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 Input- Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external addres...