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XBUF CPLL SPLL UPLL OSC. CPUCLK CLKA CLKB CLKC CLKD MUX OE CLKF /1,2,4 /1,2,3,4,5,6 /8,10,12,13 /20,24,26,40/48,52,96,104 /2,3,4 /1,2,4,8 (8 BIT) (8 BIT) (10 BIT) Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-07189 Rev. *C Revised September 16, 2008 [+] Feedback CY2291 Pinouts Pin Definitions Figure 1. CY2291- 20-pin SOIC 32XOUT 32K CLKC VDD GND XTALIN XTALOUT XBUF CLKD CPUCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 32XIN VBATT SHUTDOWN/OE S2/SUSPEND VDD S1 S0 CLKF CLKA CLKB Name Pin Number Description 32XOUT 1 32.768-kHz crystal feedback. 32K 2 32.768-kHz output (always active if VBATT is present). CLKC 3 Configurable clock output C. VDD 4, 16 Voltage supply. GND 5 Ground. XTALIN[1] 6 Reference crystal input or external reference clock input. XTALOUT[1, 2] 7 Reference crystal feedback. XBUF 8 Buffered reference clock output. CLKD 9 Configurable clock output D. CPUCLK 10 CPU frequency clock output. CLKB 11 Configurable clock output B. CLKA 12 Configurable clock output A. CLKF 13 Configurable clock output F. S0 14 CPU clock select input, bit 0. S1 15 CPU clock select input, bit 1. S2/SUSPEND 17 CPU clock select input, bit 2. Optionally enables suspend feature when LOW.[3] SHUTDOWN/OE 18 Places outputs in three-state[4] condition and shuts down chip when LOW. Optionally, only places outputs in three-state[4] condition and does not shut down chip when LOW. VBATT 19 Battery supply for 32.768-kHz circuit. 32XIN 20 32.768-kHz crystal input. Notes 1. For best accuracy, use a parallel-resonant crystal, CLOAD . 17 pF or 18 pF. 2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal). 3. Please refer to application note “Understanding the CY2291, CY2292 and CY2295” for more information. 4. The CY2291 has weak pull downs on all outputs (except 32K). Hence, when a three-state condition is forced on the outputs, the output pins are pulled LOW. Document #: 38-07189 Rev. *C Page 2 of 12 [+] Feedback CY2291 Operation The CY2291 is a third-generation family of clock generators. The CY2291 is upwardly compatible with the industry standard ICD2023 and ICD2028 and continues their tradition by providing a high level of customizable features to meet the diverse clock generation needs of modern motherboards and other synchronous systems. All parts provide a highly configurable set of clocks for PC motherboard applications. Each of the four configurable clock outputs (CLKA–CLKD) can be assigned 1 of 30 frequencies in any combination. Multiple outputs configured for the same or related[3] frequencies have low (<500 ps) skew, in effect providing on-chip buffering for heavily loaded signals. The CY2291 can be configured for either 5V or 3.3V operation. The internal ROM tables use EPROM technology, allowing full customization of output frequencies. The reference oscillator has been designed for 10 MHz to 25 MHz crystals, providing additional flexibility. No external components are required with this crystal. Alternatively, an external reference clock of frequency between 1 MHz and 30 MHz can be used. Customers using the 32-kHz oscillator must connect a 10-MW resistor in parallel with the 32-kHz crystal. Output Configuration The CY2291 has five independent frequency sources on-chip. These are the 32-kHz oscillator, the reference oscillator, and three Phase-Locked Loops (PLLs). Each PLL has a specific function. The System PLL (SPLL) drives the CLKF output and provides fixed output frequencies on the configurable outputs. The SPLL offers the most output frequency divider options. The CPU PLL (CPLL) is controlled by the select inputs (S0–S2) to provide eight user-selectable frequencies with smooth slewing between frequencies. The Utility PLL (UPLL) provides the most accurate clock. It is often used for miscellaneous frequencies not provided by the other frequency sources. All configurations are EPROM programmable, providing short sample and production lead times. Please refer to the application note “Understanding the CY2291, CY2292, and CY2295” for information on configuring the part. Power Saving Features The SHUTDOWN/OE input three-states the outputs when pulled LOW (the 32-kHz clock output is not affected). If system shutdown is enabled, a LOW on this pin also shuts off the PLLs, counters, the reference oscillator, and all other active components. The resulting current on the VDD pins are less than 50 .A (for Commercial Temp. or 100 .A for Industrial Temp.) plus 15 .A max. for the 32-kHz subsystem and is typically 10 .A. After leaving shutdown mode, the PLLs have to re-lock. All outputs except 32K have a weak pull down so that the outputs do not float when three-stated.[4] The S2/SUSPEND input can be configured to shut down a customizable set of outputs and/or PLLs, when LOW. All PLLs and any of the outputs except 32K can be shut off in nearly any combination. The only limitation is that if a PLL is shut off, all outputs derived from...