Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and output ring. “Boundary Scan Order” on page

SRAM uses rising edges only ¦ Echo clocks (CQ and CQ) simplify data capture in high speed systems ¦ Data valid pin (QVLD) to indicate valid data on the output ¦ Synchronous internally self-timed writes [1] ¦ Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD ¦ HSTL inputs and variable drive HSTL output buffers ¦ Available in 165-ball FBGA package (15 x 17 x 1.4 mm) ¦ Offered in both in Pb-free and non Pb-free packages ¦ JTAG 1149.1 compatible test access port ¦ Delay Lock Loop (DLL) for accurate data

Max Unit VIH Input HIGH Voltage VREF + 0.2 – VDDQ + 0.24 V VIL Input LOW Voltage –0.24 – VREF – 0.2 V Notes 15. Power up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 16. Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175. < RQ < 350.. 17. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175. < RQ < 350.. 18. VREF (min) = 0.68V or 0.46VDDQ, whichever is larger. VREF (max) = 0.95V or 0.54VDDQ, whic

Write Operations Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock (K). The address presented to Address inputs is stored in the Write Address register. On the following K clock rise, the data presented to D[17:0] is latched and stored into the 18-bit Write Data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the Negative Input Clock (K), the information presented to D[17:0] is also stored into the