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15 RSVD Reserved. 14:8 VID_FF_ THRESH Video FIFO Threshold. Watermark level for setting the video FIFO threshold. This value also determines when the secondary priority is used during a write request. If the FIFO WORD count exceeds this value, the secondary priority ID is used. An INT or SMI can also be generated if this threshold is exceeded. Threshold value. 0-127 Linear mode: Y buffer depth is 192 QWORDs. Planar mode: Y,U,V buffer depths are all 64 QWORDs 7:5 SYNC_TO_PIN Sync Select. Selects signal timing for VIP_VSYNC pin. 000: 0 (output disabled). 001: Select vsync_in from DC. 010: Select vsync_in from DC (inverted). 011: Select bit 17 of Status register (VIP Memory Offset 08h). 100-111: 0. 4:3 FIELD_TO_DC Field to DC Select. Selects signal for field_to_vg. 00: Field input. 01: Inverted field input. 10: LSB of page being written (indicates which page is currently active). 11: Inverted LSB of page being written. 2:0 SYNC_TO_DC VSYNC Select. Selects signal timing for VIP_VSYNC output to the DC. 000: Sync from pin. 001: Inverted sync from pin. 010: VBLANK. 011: Inverted VBLANK. 100: Field. 101: Inverted field. 110: When vip_current_line = target_line. 111: 0. AMD Geode™ LX Processors Data Book 33234H Video Input Port Register Descriptions 6.10.2.3 VIP Status (VIP_STATUS) VIP Memory Offset 08h Type R/W Reset Value xxxxxxxxh VIP_STATUS Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 APC RSVD FPE RSVDDPCSOBRNURSVDMSG_BERRB2_FULLB1_FULL RSVD GLWCFE RSVD F V RUN_STATUS VIP_STATUS Bit Descriptions Bit Name Description 31:24 APC (RO) Ancillary Packet Count (Read Only). Number of ancillary packets available in the ancillary buffer in system memory. This count is incremented each time an ancillary packet is received. It gets decremented when a 1 is written to the DPC bit (bit 18). 23 RSVD Reserved. 22:20 FPE (RO) FIFO Pointer Error (Read Only). These bits indicate if the FIFO pointers are misaligned at the point when the base registers are updated. A 1 indicates that the pointers may be misaligned, which could result in an horizontal image shift. These bits are valid only when VBI data reception is disabled. INT15 is generated when any of these bits go active. [22] - B FIFO. [21] - R FIFO. [20] - Y FIFO. 19 RSVD Reserved. 18 DPC (WO) Decrement Ancillary Packet Count (Write Only). Writing a 1 to this bit causes the ancillary packet count to be decremented by 1. 17 SO (WO) Sync Out (Write Only). Writing a 1 to this bit causes a 0-1-0 transition on the VIP_VSYNC pin (32 GLIU clocks). 16 BRNU (RO) Base Register Not Updated (Read Only). 0: All base registers are updated. 1: One or more of the base registers have been written but have not yet been updated. Note: The following base registers are updated at a start-of-frame event. TASK_A_VID_EVEN_BASE, TASK_A_VID_ODD_BASE, TASK_A_VBI_EVEN_BASE, TASK_A_VID_ODD_BASE, TASK_A_VID_EVEN_BASE, TASK_A_VID_ODD_BASE, TASK_A_VBI_EVEN_BASE, TASK_A_VID_ODD_BASE The start-of-frame event occurs when entering a vertical blanking interval during the Odd field (for interlaced video) or when entering any vertical blanking interval (non-interlaced video). Since the base pointers are initialized to 0 at reset, a start-of-frame event MUST occur before enabling VIP to receive data. Otherwise, VIP will save the first video frame to address 0 in system memory. One way of insuring this is to initialize VIP to receive video data with the RUN_MODE bits (VIP Memory Offset 00h bits [7:5]) set to 0. This enables the VIP input interface, but it will not capture video. Poll this bit until the internal base register updates have occurred. The RUN_MODE control can then be programmed to start capturing data on the next line/field/frame boundary. 15 RSVD Reserved. AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions 33234H VIP_STATUS Bit Descriptions (Continued) Bit Name Description 14 MSG_BERR Message Buffer Error. 0: No error. 1: Message buffer was overwritten. This occurs when both msg buffers are full and a msg/dstrm packet is received. Writing a 1 to the bit resets it to 0. 13 B2_FULL MSG Buffer 2 Full. 0: Buffer 2 empty. 1: Buffer 2 full. Writing a 1 to the bit resets it to 0. 12 B1_FULL MSG Buffer 1 Full. 0: Buffer 1 empty. 1: Buffer 1 full. Writing a 1 to the bit resets it to 0. 11:10 RSVD Reserved. 9 GLWC GLIU Writes Completed. 0: VIP has outstanding GLIU transactions. 1: VIP has completed all outstanding GLIU transactions. 8 FE VIP FIFO Empty. 0: VIP FIFO is NOT empty. 1: VIP FIFO is empty. 7:5 RSVD Reserved. 4 F (RO) Field Indication (Read Only). Indicates current status of field being received. 0: Odd field is being received. 1: Even field is being received. 3 V (RO) VBLANK Indication (Read Only). Indicates current status of VBLANK being received. 0: Active video. 1: Vertical blanking. 2:0 Run Status (RO) Run Status (Read Only). Indicates active data types received. Bit 2: Indicates that an ancillary packet has been received....

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