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VG_CK is bit 20 in the Display Configuration register (VP Memory Offset 0008h). Note 2. GFX_INS_VIDEO is bit 8 in the Video De-interlacing and Alpha Control register (VP Memory Offset 0098h). ALPHAx_COLOR_REG_EN are bit 24 in the Alpha Window Color registers (VP Memory Offsets 0D0h, 0F0h, and 110h). Note 3. x = Don’t care. 6.7.5.2 Gamma RAM Either the graphics or video stream can be routed through an integrated palette RAM for gamma-correction of the data stream or (for video data) contrast/brightness adjustments. A bypass path is provided for either the graphics or video stream (depending on which is sent through the gamma RAM). 6.7.5.3 Video Processor Module Display Interface The Video Processor module connects directly to either the internal CRT DACs, or provides a standard digital TFT interface. 6.7.5.4 Video Interface The VP uses a two-wire protocol to control the sequence of data on the video port. This protocol consists of VID_VAL and VID_RDY. VID_VAL indicates the DC has placed valid data on the 32-bit VID_DATA bus. VID_RDY indicates the VP is ready to accept video data for the next video source line. The VP typically starts fetching video data five scan lines before the data is required for display. AMD Geode™ LX Processors Data Book 33234H Video Processor 6.7.6 Video Output Port 6.7.6.1 Functional Overview The Video Output Port (VOP) receives YUV 4:4:4 encoded data from the VP and formats the data into a video-stream that is BT.656) or BT.601 compliant. Output from the VOP goes to either a VIP or a TV encoder. The VOP must be BT.656/BT.601 compliant since its output may go directly (or indirectly) to a display. Slave Interface Data from Blender VOP Registers 4:4:4 to 4:2:2 Converter CRC Generator VOP Data Out VOP Data Formatter 6.7.6.2 Supported Features • VIP 2.0 (level I and II) with VIP 1.1 compatibility mode, BT.656 mode supported • Support for VIP 2.0 NON_INT bit (REPEAT and EXT_FLAG not supported) • BT.601 mode supported • VBI data supported (no support for ancillary data) Figure 6-29. VOP Internal Block Diagram AMD Geode™ LX Processors Data Book Video Processor 33234H 6.7.6.3 HBLANK and VBLANK Signals VBLANK is a function of the vertical line number and the HBLANK and VBLANK signals are different from HSYNC horizontal pixel position. Figures 6-30 to 6-34 show the for- and VSYNC. The HSYNC and VSYNC signals are only mation of these signals using a 525-line NTSC video win- active for a portion of the blanking time, while the HBLANK dow. and VBLANK signals are active through the entire time. HBLANK is a function of horizontal pixel position, while Pixel Position 858 Line Number Frame 1 525 1 V = 1 V = 0 V = 1 V = 0 20 264 283 Frame 0 (continued) Frame 0 Figure 6-30. 525-Line NTSC Video Window 721 858 001 720 Pixel Position L# L# + 1 Line Number HBLANK VBLANK Figure 6-31. HBLANK and VBLANK for Lines 20-262, 283-524 AMD Geode™ LX Processors Data Book 33234H Video Processor 721 858 001 720 Pixel Position 244 245 Line Number HBLANK VBLANK Figure 6-32. HBLANK and VBLANK for Lines 263, 525 721 858 001 720 Pixel Position L# L# + 1 Line Number HBLANK VBLANK Figure 6-33. HBLANK and VBLANK for Lines 1-18, 264-281 721 858 001 720 Pixel Position 294 001 Line Number HBLANK VBLANK Figure 6-34. HBLANK and VBLANK for Lines 19, 282 AMD Geode™ LX Processors Data Book Video Processor 33234H 6.7.6.4 Interface to Video Processor The output from the Video Processor is connected via a 24-bit bus. Bytes on this bus are aligned as shown below: [23:16] Y [15:8] Cr (V) [7:0] Cb (U) The VOP takes this 24-bit 4:4:4 data bus and converts it to a 16-bit 4:2:2 data bus (the Y component on the high byte, the U/V components alternating on the low byte). The VOP provides three different methods for translating from 4:4:4 to 4:2:2 data depending on the value of the mode select bits from the VOP Configuration register (VP Memory Offset 800h[5:4]) as shown in Table 6-61. Table 6-61. VOP Mode Mode Bits Description 0 00 4:2:2 Co-sited (Recommended) 1 01 4:2:2 Interspersed 2 10 4:2:2 Interspersed, free-running Mode 0: 4:2:2 Co-sited In this mode, the U/V samples are dropped on alternating sample sets, resulting in the below representation. Mode 1: 4:2:2 Interspersed In this mode, adjacent pairs of U/V sample data are averaged, with the U/V samples coming from the same adjacent sample sets. Luminance (Y) Samples Chromance (U,V) Samples Sampling algorithm: Y, U, V : 4:4:4 Input data Y’, U’, V’ : 4:2:2 Sampled data Y1’ = Y1, U1’ = (U1+U2)/2, V1’ = (V1+V2)/2 Y2’ = Y2 Y3’ = Y3, U3’ = (U3+U4)/2, V3’ = (V3+V4)/2 etc. Mode 2: 4:2:2 Interspersed (free-running) This mode is the same as Mode 1 with the exception that the U sample is averaged between the first two samples, and the V sample is averaged between the second and third samples. Luminance (Y) Samples Chromance (U,V) Samples Sampling algorithm: Y, U, V : 4:4:4 Input data Y’, U’, V’ : 4:2:2 Sampled data Y1’ = Y1, U1’ = U1, V1’ = V1 Y2’ = Y2 Y3’ = Y3, U3’ = U3, V3’ = V3 etc. Luminance (Y)...

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