Absolute Maximum Ratings this circuit. For proper operation, VIN and VOUT should be constrained to the range, VSS < (VIN or VOUT) < VDD. All digital inputs are tied high or low internally. Refers to electrical specifications for operating supply range. Parameter Description Min. Max. Unit VDD Operating Voltage 3.0 6.0 VDC VIRvss Input, relative to VSS –0.3 VDD + 0.3 VDC VORvss Output, relative to VSS –0.3 VDD + 0.3 VDC TOP Temperature, Operating 0 +70 °C TST Temperature, Storage –65 +150 °C TJ T

*F Page 4 of 12 [+] Feedback FS781/82/84 Table 4. Modulation Rate Divider Ratios S1 S0 Input Frequency Range (MHz) Modulation Divider Number 0 0 6 to 16 120 0 1 16 to 32 240 1 0 32 to 66 480 1 1 66 to 82 720 SSCG Modulation Profile The digital control inputs S0 and S1 determine the modulation frequency of FS781/2/4 products. The input frequency is divided by a fixed number, depending on the operating range that is selected. The modulation frequency of the FS78x can be determined from Table 4. To

outputs • 6- to 82-MHz operating frequency range • Modulates external clocks including crystals, crystal oscillators, or ceramic resonators • Programmable modulation with simple R-C external loop filter (LF) • Center spread modulation • 3V-5V power supply • TTL-/CMOS-compatible outputs • Low short-term jitter • Low-power Dissipation — 3.3 VDC = 37 mW – typical — 5.0 VDC = 115 mW – typical • Available in 8-pin SOIC and TSSOP packages Applications • Desktop/notebook computers • Printers, copiers,

terminated lines ¦ Low operating current ¦ 24-pin SOIC package ¦ Jitter:<200 ps peak to peak, <25 ps RMS Functional Description The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer low skew system clock distribution. These multiple output clock drivers optimize the timing of high performance computer systems. Each of the eight individual drivers can drive terminated transmission lines with impedances as low as 50.. They deliver minimal and specified output skews and full swing logic levels (CY

BiCMOS technology Functional Description The CYV15G0104TRB Independent Clock HOTLink II™ Serializer and Reclocking Deserializer is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link. The transmit and receive channels are independent and can operate simultaneously at different rat

. *B Revised April 11, 2006 [+] Feedback CY25818/19 . Pin Description Pin Name Description 1 XIN/CLK Clock, Crystal, or Ceramic Resonator Input Pin. 2 Vss Power Supply Ground. 3 S0 Digital Spread% Control Pin. 3-Level input (H-M-L). Default = M. 4 SSCLK Modulated Spread Spectrum Output Clock. The output frequency is referenced to input frequency. Refer to Table 2 for the amount of modulation (Spread%). 5 REFCLK Unmodulated Reference Clock Output. The unmodulated output frequency is the same as t

Notes 9. Jitter measured at crossing points and is the absolute value of the worst case deviation. 10. Measured at crossing points. 11. If input modulation is used; input modulation is allowed but not required. 12. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew that cannot exceed the skew generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%. 13. VOX

Low power, 350 nA RTC current . Capacitor or battery backup for RTC ¦ Watchdog timer ¦ Clock alarm with programmable interrupts ¦ Hands off automatic STORE on power down with only a small capacitor ¦ STORE to QuantumTrap™ initiated by software, device pin, or on power down ¦ RECALL to SRAM initiated by software or on power up ¦ Infinite READ, WRITE, and RECALL cycles ¦ High reliability . Endurance to 200K cycles . Data retention: 20 years at 55°C ¦ Single 3V operation with tolerance of +20%, –10

Aggregate throughput of up to 12 Gbits/second ¦ Second-generation HOTLink® technology ¦ Compliant to multiple standards . SMPTE-292M, SMPTE-259M, DVB-ASI, Fibre Channel, ESCON, and Gigabit Ethernet (IEEE802.3z) . 10 bit uncoded data or 8B/10B coded data ¦ Truly independent channels . Each channel is able to: • Perform reclocker function • Operate at a different signaling rate • Transport a different data format ¦ Internal phase-locked loops (PLLs) with no external PLL components ¦ Selectable dif

*B Revised October 26, 2005 [+] Feedback CY25566 Pin Description Pin Name Type Description 1 XIN/CLKIN I Clock or Crystal connection input. Refer to Table 1, Table 2, and Table 3 for input frequency range selection. 2 REFOFF I Input pin enables REFOUT clock at pin 3. REFOFF 400K. internal pull-up resistor. Logic “0” enables REFOUT, logic “1” disables REFOUT. Default = disabled. 3 REFOUT O Buffered, non-modulated output clock derived from XIN/CLKIN input frequency. There is a 180° phase shift fro